This invention relates to input delay equalization in pipelined accumulator systems and, more particularly, to input delay equalization emulation in high speed, phase modulated direct digital synthesis (DDS) systems.
At the core of pipelined DDS systems is an accumulator block using replications of a register element that stores the sum bits and the carry bit in flip-flops. Because of the pipelined architecture, the output sum bits from each stage must be delayed through as many register elements as there are pipelined stages between the most significant stage and the particular stage of concern. After this "delay equalization", the sum can be used to address a ROM, RAM or other suitable memory block that stores digitized values of a sine, cosine, or other waveform. Data retrieved from the memory block may be used in various ways, for example to drive D/A circuitry to form an analog output waveform.
To achieve phase modulation of an output waveform, an increment value of the accumulator must be changed regularly. Traditionally, a loadable down counter and multiplexer arrangement have been used to regularly change the accumulator increment. For example, one 2:1 multiplexer ("mux") is provided for each bit of the accumulator. One input of each multiplexer receives a corresponding bit of a NEW C word (C for Complete phase increment or accumulation value), while the other input of each multiplexer receives a corresponding bit of a NEW D word (D for Delta phase increment or phase modulated value). In phase modulated mode, each time the counter completes a predetermined "repeat value" number of counts, corresponding to an offset, all of the multiplexers are switched from sourcing NEW C bits to sourcing NEW D bits for one clock cycle, and then switched back to sourcing NEW C.
Because the accumulator is pipelined, changes to the increment value, i.e. the 2:1 multiplexer output data, must be "delay equalized" in a manner similar to the outputs, i.e., using registers. All bits of the input increment value must be delay equalized, even though the only output bits that have to be delay equalized are those that form the ROM/RAM address. The necessary increment value delay equalization circuitry thus is very large. The number of flip-flops needed in this architecture is given by the formula: EQU (Q * (N.sup.2 +N))/2
where Q is the number of bits per pipelined stage, and N is the number of pipelined stages. Thus, for example, a 24 bit accumulator with 2-bit pipelined segments requires 156 flip-flops for input delay equalization alone. These numbers of flip-flop circuits demand substantial circuit area and power.
What is needed is a way to reduce the number of flip-flops required in the input delay equalization area.